1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for controlling lattice defects at a junction, and a method for forming lightly doped drain (LDD) or source/drain (S/D) regions of a CMOS device that incorporates the above method.
2. Description of the Related Art
As semiconductor devices are continuously scaled down, the affect of lattice defects in the semiconductor substrate becomes more and more significant. The lattice defects of a semiconductor material include mainly dislocation and stacking fault defects, which are caused by complex interaction of crystallization defects, metallic ions in the substrate, stress induced by ion implantation and the process thermal cycle. The major problem caused by the defects is extra current leakage, which is particularly large when the defects cross the LDD junction, S/D junction or well junction so that the circuit functionality or the yield is impacted.
Therefore, it is highly desirable to develop a method for reducing the dislocation and stacking fault defects in a semiconductor substrate. So far, there is no effective method for controlling formation of the defects.